1. Technical Field
The present invention relates to a method for the automatic regulation of the reference sources in a non-volatile memory device, for example a flash memory. More specifically, one embodiment of the invention relates to a method for the automatic regulation of the reference sources in a non-volatile memory device incorporating a plurality of sources or signal generators or reference potentials and for which a functionality testing step is provided at the end of the production process by means of a test machine removably connected to some terminals of the device. One embodiment of the invention particularly, but not exclusively, relates to a non-volatile memory device of the Flash EEPROM type and the following description is made with reference to this specific field of application for simplifying the illustration only.
2. Description of the Related Art
As is well known in this specific technical field, for the correct operation of a flash memory, different signals may serve as references for most of the inner circuitry. In particular, sample signals may represent a constant reference in voltage or in current, or variable signals having square wave but fixed frequency.
All these signals are produced inside by using different circuit techniques for their generation, for example the use of sources based on the energy gap between the conduction and valence band of the silicon is known to obtain stable signals in voltage, this category of circuits are called band gaps and provide excellent performances to supply stable references in voltage. The stability is ensured both when the temperature varies and when the supply voltage varies.
Similar solutions are adopted for producing reference currents. Often, these sources are in turn used for producing signals serving as a base for the clock times of different inner circuits (for example clocks for charge pumps, clocks for the embedded micro-controller etc . . . ).
Unfortunately, to obtain stable reference signals the sole, correct design of the references is not enough since some inevitable layout asymmetries of the structures constituting them, as well as variations of the technological processes, invalidate their precision. For these reasons, before starting the flash memory test operations, it may be prudent to suitably regulate all the generators of the inner references by acting on suitable configuration registers inside the memory.
At present, the regulation of the reference sources is carried out at the end of the manufacturing process of the memory integrated circuit and by means of the intervention of a test machine on the memory. More in particular, the value of a signal S to be regulated by means of a suitable procedure is read. The test machine processes the measurement and determines the correction to be carried out. The correction is then set in the memory configuration registers.
This solution is schematized in the herewith annexed FIG. 1 wherein the temporary coupling is shown between a test machine and a generic memory device to be tested, shown as DUT (Device Under Test).
At this point, the reading of the regulated width is repeated for establishing if the measured value is acceptable, i.e., if:
                                  S          Δ                et            ⁢              S                              toll            _                    ≤                              t    ⁢                  ⁢          measured      arg      is equal to that provided when designing apart from a predetermined tolerance Δtoll. In case the regulation has not succeeded the process is repeated for a predetermined number of times, afterwards the device is discarded.
As regards instead the measuring and the regulation of a clock source, in the prior art there already exists a solution shown by way of example in FIG. 2.
In this solution a clock circuit 30, which is to be measured, is enabled by means of a counter 31, under the supervision of a logic 32. The counter 31 which takes care of counting the clock periods comprised in a known ΔT is set by the test machine by means of the enable signal.
Through the output pads of the memory device the n-bits of the counter 30 are read and the detected frequency FCLOCK=1/(N ΔT) happens to be the clock target frequency; in the contrary case, action is taken on the configuration bits and the measuring is repeated. FIG. 2A schematically shows how this frequency is detected.
In case the right configuration is not found for obtaining the target frequency, the device is discarded.
In general, this way of proceeding shows different limits:
The process requires the intervention of an external test machine able to read and to make decisions on the correcting actions to be taken.
The corrections to be actuated are different from device to device, thus the test machine must question the single device and perform an ad hoc correction for it.
Consequently, the test machine is obliged to serialize the controls with subsequent decrease of productivity.